The widespread use of personal communication products, such as cell phones and wireless LANs, has created a demand for semiconductor devices which can provide certain operational characteristics specific to these devices. One of these operational characteristics relates to the power dissipated in the semiconductor devices. The conventional method to reduce the power dissipation is to use a power supply voltage of three volts or less. However, certain portions of the electronics, such as the RF transmitters, require power devices that can handle higher voltages and currents than are not present in the rest of the electronic circuitry. This requirement is exacerbated by the demand for ever smaller products thus providing a strong incentive for combining complementary power devices on the same substrate as other portions of the electronics. The lateral double diffused MOSFET (LDMOS) transistor is virtually the only silicon device to meet these requirements.
LDMOS transistors know in the art usually use a drift region to provide the relatively high breakdown voltages required of these devices. However such drift regions increase device resistance and take up space on a semiconductor chip thus requiring a significantly larger chip area than needed for convention MOSFETs.
In addition, most of these prior art LDMOS transistors have relatively low DC transconductance that also is significantly degraded in the frequency ranges used in many of the personal communication products, have power loss in the device due to capacitances, junction leakage and substrate loss, and can have reliability problems arising from the hot carrier effect.
Therefore, it can be appreciated that a LDMOS transistor which can provide improvements in some or all of these areas over the currently known LDMOS transistors is highly desirable